Field of the Invention
The present invention generally relates to computer science and, more specifically, to techniques for supporting demand paging.
Description of the Related Art
A typical computer system includes a central processing unit (CPU) and one or more parallel processing units (PPUs). Some advanced computer systems implement a unified virtual memory architecture common to both the CPU and the PPUs. Among other things, the architecture enables the CPU and the PPUs to access a physical memory location using a common (e.g., the same) virtual memory address, regardless of whether the physical memory location is within system memory or memory local to the PPU.
In operation, a process executing on a processing unit (e.g., either the CPU or the PPU) accesses data stored in physical memory via a virtual memory address. To execute the memory access, the memory management unit (MMU) associated with the processing unit attempts to translate the virtual memory address to a physical memory address. If the translation is successful, then the processing unit uses the physical address to access the data stored in a physical memory. However, in some cases, the memory access request may not be successful, such as when the page table associated with the processing unit does not include the necessary address mapping or when the processing unit does not have permission to access the physical memory with the type of memory access requested. In general, if an MMU is unable to translate a virtual memory address to an appropriate physical memory address, then the MMU generates a page fault.
With some processing units, unsuccessful memory access requests can be fatal, meaning that the process executing on the processing unit is not able to execute as intended when a page fault occurs. “Demand paging” addresses this issue. With demand paging, if a process is unable to initially access data via a virtual memory address, then steps are taken to remedy the page fault and the process executes as intended.
In one approach to supporting demand paging, a unit within the computer system that performs an unsuccessful memory access stalls while the computer system responds to the page fault. After the computer system maps the virtual memory address to an appropriate location in physical memory or provides the necessary access permission, the faulting unit retries the memory access. For example, suppose that a compute engine included in the PPU were to attempt to access data via a virtual memory address, and the PPU MMU was unable to translate the virtual memory address to a physical memory address. In such a scenario, the PPU MMU would generate a page fault and the compute engine would stall. Fault-handling mechanisms within the computer system would remedy the page fault and, subsequently, the compute engine would perform the memory access successfully.
One drawback of the above approach is that stalling faulting units risks stalling the units required to remedy the page fault. Notably, if a unit required to remedy a page fault stalls, then the page fault may not be properly remedied. For instance, if a copy engine were to encounter a page fault, then the copy engine would be unable to perform operations to remedy the page fault, such as page table update operations. Consequently, stalling faulting units enables demand paging only for those units that are not involved in remedying page faults.
As the foregoing illustrates, what is needed in the art is a more effective approach to supporting demand paging.